1. Field of the Invention
This invention relates to a method for optimizing electromagnetic interference (EMI) and a method for analyzing the electromagnetic, and more particularly to a method for optimizing the EMI by simulation at a high speed and with great accuracy for a large scale and high speed driving LSI (large scale semiconductor integrated circuit).
2. Description of the Related Art
The LSI has been widely used in not only a computer but also a communication device such as a portable telephone, a household appliance, a toy, a motorcar, etc. However, the EMI emitted form these devices has become problematic as (EMI) for a receiver such as a television/radio and a cause for malfunction of other systems. In order to overcome these inconveniences, a measure such as filtering or shielding has been made for the entire device. However, from the standpoint of the increase in the number of components, increase in cost, difficulty in the measure for a product, etc., noise suppression in an LSI package itself has been eagerly demanded.
Under such a circumstance, in each of the products, the LSI is placed as a key device. In order to assure the ability to compete, the large-scaling and speed-up of the LSI have been demanded. As the product cycle becomes short, in order to satisfy these demands, the automation of LSI designing is indispensable. Hence, necessity of adopting synchronous designing has risen as a condition for introducing the present designing automation technology. However, the entire circuitry operates synchronously with a reference clock, and in the case of the LSI designed in a large scale and driven at a high speed, the instantaneous current becomes very large, thereby leading to an increase in the EMI.
This invention relates to a simulation technique which can maintain the large-scaling and speed-up of the LSI and permits EMI evaluation indispensable to reduce the EMI.
The noise given by the LSI is roughly classified into radiation noise and conduction noise. The noise radiated directly from the LSI includes the noise radiated from the internal wiring of the LSI. However, the internal wiring is not so large as an antenna. As the operating frequency of the LSI is improved, the noise radiated directly from the LSI may be problematic in the future. However, at present, the radiation noise within the LSI is not problematic.
On the other hand, the conduction noise influences the other devices on a printed board through direct connection such as wires within the LSI, a lead frame, package or wiring on the printed board, and noise is radiated from a source or antenna of these connecting passages. The antenna of the connecting passage is much larger than the internal wiring of the LSI so that it constitutes a dominant element from the standpoint of the EMI.
The passage of the conduction noise from the LSI includes a power source and a signal. However, in the nearby electromagnetic field, a change in the current from the power source may be dominant as noise radiated from the antenna of the power source line. In many case, the package or measurement system as well as the power source is also problematic.
For example, in recent years, the EMI noise in the LSI has become an important problem so that the method of measuring the EMI noise in the LSI is being standardized by the IEC (International Electric Standard Committee). Analysis techniques such as magnetic probe technique or VDE technique have been proposed. Thus, LSI vendors can appeal the EMI noise performance of their own LSI for customers. The customers also can absolutely compare the LSIs from the standpoint of the EMI noise. Further, if the standard measuring technique prevails, the standard of the EMI noise of the LSI will be established.
However, conventionally, since the measurement system (measuring device and printed board for measurement) has not be taken into consideration, in the stage of developing the LSI, whether or not the LSI satisfies the above standard could not be determined.
Further, with respect to a signal, although there is a case where xe2x80x9cringing overshootxe2x80x9d occurring when the signal changes is problematic, in many cases, the fact that a change in a power source level within the LSI conducts as a signal waveform is problematic. It seems that the noise which conducts or radiates in either passage of the power source or signal is strongly correlated with a change in the power source current.
An explanation will be given of a power source current for a CMOS circuit using a simple inverter circuit. When an input voltage to the inverter varies, a load capacitor charging/discharging current which is a main power source current flows. A tunneling current also flows additively. Where such a CMOS circuit is designed, synchronization is carried out because of limitation of using an automated designing tool. However, owing to the synchronization, the circuits in the entire LSI operate simultaneously, and hence a peak current in the power source is generated in synchronism with a reference clock. In addition, in order to realize the high speed or shorten the period, the transistor size is increased to implement the charging/discharging in a short time. This increases the peak current. As a matter of course, large-scaling of the LSI increases the power source current in the entire LSI. In this way, the peak current of the power source increases and the power source current varies abruptly. This abrupt variation increases a harmonic component and leads to an increase in the EMI.
To execute accurate simulation of the variation in the power source current which may be a main cause of the EMI is efficient as evaluation of the EMI in the LSI.
Meanwhile, conventionally, the current simulation technique of conducting a current analysis in a transistor level has been used.
FIG. 46 is a block diagram showing a processing flow of a conventional EMI analyzing method using the current analysis technique in a transistor level. This method includes steps of layout parameter extraction (hereinafter referred to as LPE) 4603 from the layout information of an LSI which is an analysis object; circuit simulation 4606 about a switch level netlist; current source modeling processing 4608; power source line LPE processing 4610; transient analysis simulation 4612; and FET processing.
Referring to FIG. 46, an explanation will be given of the respective steps.
In step 4603, using inputs of: the layout data 4601 of a semiconductor integrated circuit which is an object for EMI analysis and an LPE rule 4602 which defines a transistor element or various line parasitic elements (resistor, capacitor, etc.), the parameter value of each element, and an output format of their extracted result, on the basis of the LPE rule 4602, the parameter of each element in the layout data 4601 is computed to create a netlist 4604. Incidentally, in this step, the parasitic element of a power source (and ground) is not used as the object of extraction.
In step 4606, using inputs of the netlist 4604 created from the above step 4603 and a test pattern 4605 for recreating a desired logic operation in an analysis object circuit, according to the operating status of an internal circuit, a charging/discharging current for charging/discharging a load capacitance, a tunneling current, etc. are computed to create current waveform information 4607 for each transistor. Incidentally, the first processing in this step is carried out on the assumption that the power source (and ground) potential is an ideal potential with no change.
In step 4608, an input of current waveform information 4607 for each transistor created in the previous step 4606 is modeled into a format applicable to later step 4612 to create current source element model information 4609. Incidentally, in order to reduce the burden of processing in the later step 4712, the technique of modeling the current source element for each functional circuit block constructed of a plurality of transistors is generally adopted.
Step 4610 will not be explained here because this step is different from step 4603 in only that as an object to be extracted, the transistor element or various kinds of interconnect line""s parasitic elements are replaced by a parasitic element (resistor, decoupling capacitor, etc.) for the power source and ground line.
In step 4612, using inputs including the current element model information created in the step 4608, power source (and ground) line netlist 4611 created in the step 4610 and impedance (resistance, capacitance or inductance) 4616 of a wire or lead frame, the analysis using a transient analysis simulator represented by SPICE is carried out to create a power source voltage drop result 4617 which is a computed result of a voltage source change in the circuit to be analyzed.
Thereafter, the reprocessing of the step 4606 is carried out. In this case, the first processing of the step 4606 has been carried out on the assumption that the power source (and ground) potential is an ideal potential with no change. However, now, using an input of the power source voltage drop result 4617 created in the step 4612, the current waveform information 4607 for each transistor taking a power source voltage change into consideration is created again. Likewise, the reprocessing of the steps 4608 and 4612 is carried out again.
The loop processing of the steps 4606, 4608 and 4612 is repeated plural times to create a current waveform result 4613 with the power source voltage change reproduced with high accuracy.
In step 4614, an input of the current waveform result is subjected to fast Fourier transform (referred to as FFT) so that frequency spectrum analysis can be carried out, thereby providing an EMI analysis result 4615.
In the prior art as described above, although the inspection accuracy greatly depends on a combination of the LPE processing 4603, power source line LPE processing 4610 and the current source modeling processing 4608, the analysis accuracy in a certain level can be expected. However, since such a current analysis in the transistor level uses the transient analysis simulator represented by SPICE, the scale of the EMI analysis object circuit is limited and the processing time therefor can be increased. With the large-scaling of a semiconductor integrated circuit, in recent years, establishment of the EMI analysis with higher abstractiveness than the transistor level and capable of performing high speed analysis has been demanded.
The large-scaling of a chip and an increase in the number of elements increase the scale of a network of power source lines so that an increase in the processing time is becoming a great obstacle against the analysis of the EMI. In order to shorten the processing time, the means for reducing the resistance/capacitance of these power lines has been proposed. However, it is limited to the gate array which provides a grid pattern of power source lines.
Even if the power source current value is subjected to the FET to perform the EMI analysis, finally, a designer must judge the FET characteristic. Such a means takes a very long time to define the origin of a cause, or cannot define it. Its direct reflection as analysis information on correction is very insufficient.
In a measuring system also, the processing time increases according to the scale and elements of the measuring system itself. This is a problem which is not negligible in analysis of the EMI.
As described above, the conventional EMI analysis system for the LSI is not sufficient from the standpoint of compatibility between consideration of decoupling by the resistance, capacitance and resistance in a power source, ground and further measurement system and high speed processing, and of quick reflection of the EMI analysis result on the LSI designing.
In recent years when the large-scaling of a semiconductor integrated circuit has progressed, establishment of the EMI analysis using a current analysis method in the gate level with higher abstractiveness than the transistor level and capable of performing high speed analysis has been demanded. Various researches for satisfying this demand have been attempted.
Further, even if the EMI analysis has been done, it is not clear from which circuit the main cause is originated. Therefore, there is a problem that the circuit to be modified in order to improve the EMI cannot be known.
Thus, the inventors of this invention have intended to provide an EMI analysis method and apparatus which can implement high speed analysis and evaluate the EMI from the LSI through simulation in such a manner that the influence of decoupling by a resistance, capacitance and an inductance in a power source and ground is reflected on computation of a power source current.
Namely, the inventors have proposed an EMI analysis method comprising the steps: of allotting a FFT analysis discrete width to each frequency band for its modeling, and of subjecting the current change information computed by the modeling step to the FFT (Japanese Patent Appln. No. 2000-63783).
This method presents a problem that it cannot represent the influence of a decoupling capacitance on the FFT result, and can represent it by only enlarging the bottom of a triangle so that it cannot be represented accurately and its effect cannot be shown.
This invention has been accomplished in view of the above circumstance, and intends to specify the origin of EMI for an LSI subjected to analysis and take an effective measure for the EMI.
The first aspect of this invention is characterized by comprising the steps of:
an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation;
a step of selecting an instance with a large quantity of noise in the EMI analyzing step; and
a step of adjusting a driving capability of the instance so that it is lowered in a degree to which a delay does not occur in a signal timing of the instance selected.
In this configuration, by selecting an instance with a large quantity of noise in the EMI analyzing step and adjusting a driving capability of the instance so that it is lowered in a degree to which a delay does not occur in a signal timing of the instance selected, the EMI can be easily optimized with good workability. Now, to lower the driving capability in a degree to which a delay does not occur means to lower the driving capability while the circuit operation is performed normally.
The second aspect of this invention, in the EMI optimizing method according to the first aspect, is characterized in that where there the instance of a first instance and a second instance having an output signal line in parallel adjacently to an output signal line of the first instance, the step of adjusting includes to adjust the driving capability of only the first instance or both of the first and the second instance so that it or they are lowered (in a degree to which the ratio of the driving capabilities to each other does not increase).
The third aspect of this invention is characterized by comprising the steps of:
an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation;
a step of selecting an instance with a large quantity of noise in the EMI analyzing step; and
a step of correcting a driving capability of the instance in such a way that an inductance is added to a local power source line communicated with the instance in a degree to which a delay does not occur in a signal timing of the instance selected.
The fourth aspect of this invention, in the EMI optimizing method according to the third aspect, is characterized in that the step of correcting includes to increase a power supply line resistance.
The fifth aspect of this invention is characterized by comprising:
an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation;
a step of selecting an aggressor instance with crosstalk; and
a step of adjusting a driving capability of the aggressor instance so that it is lowered in a degree to which a delay does not occur in a signal timing of the instance selected.
The six aspect of this invention, in the EMI optimizing method, is characterized by further comprising a step of raising the driving capability of a victim instance in a degree to which EMI noise of the victim instance is negligible.
The seventh aspect of this invention, in the EMI optimizing method according to the fifth aspect, is characterized in that where the driving capabilities of both of the aggressor instance and victim instance is lowered, their driving capabilities are set so that their ratio is not increased.
The eighth aspect of this invention is characterized by comprising:
an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation;
a step of sampling a block or instance with a large quantity of noise in the EMI analyzing step;
a step of reducing the EMI in the block or instance thus sampled according to a designing stage; and
a step of repeating a series of said consecutive steps until the quantity of EMI is made smaller than a prescribed value.
Although the measure of creating the decoupling capacitance of a chip is created presents a demerit of increasing the chip area, this configuration permits the measure to be taken at a necessary region, and hence prevents the chip area from being increased excessively.
This configuration is very effective because when the measure of changing the aspect ratio or changing the block position is adopted, the measure for the EMI which does not increase the chip area is required.
This method provides good workability because the measure can be implemented in a floorplan.
Further, the measure of changing the cell line is effective because a decoupling capacitance can be easily created at the most effective inserting position, i.e. the position nearest to the instance at issue.
Thus, the measure for the EMI can be implemented while an increase in the chip area is suppressed as far as possible.
The ninth aspect of this invention, in the EMI optimizing method according to the eighth aspect, is characterized in that the step of reducing EMI includes a first step of changing layout data at a floorplan stage.
The tenth aspect of this invention, in the EMI optimizing method according to the 8th or 9th aspects, is characterized in that the step of reducing EMI includes a second step of changing layout data at a layout stage.
The eleventh aspect of this invention, in the EMI optimizing method according to the ninth aspect, is characterized in that the first step includes the steps of:
computing a necessary quantity of decoupling capacitance from peak current information of an object block sampled in the step of sampling;
computing a quantity of insufficiency of an power source area from the necessary quantity of decoupling capacitance thus computed in the step of computing; and
changing the layout data on the basis of the quantity of insufficiency.
The twelfth aspect of this invention, in the EMI optimizing method, is characterized in that the second step includes the steps of:
computing a necessary quantity of decoupling capacitance from peak current information of an object block sampled in the step of sampling;
computing a quantity of insufficiency of an power source area from the necessary quantity of decoupling capacitance thus computed in the step of computing; and
changing the layout data on the basis of the quantity of insufficiency.
The thirteenth aspect of this invention, in the EMI optimizing method, is characterized in that the first step includes the steps of:
computing a necessary quantity of decoupling capacitance from peak current information of an object block sampled in the step of sampling;
computing a quantity of insufficiency of an power source area from the necessary quantity of decoupling capacitance thus computed in the step of computing; and
changing the layout data for a required block on the basis of the quantity of insufficiency.
The fourteenth aspect of this invention, in the EMI optimizing method according to 11, is characterized in that the step of changing the layout data is to change the aspect ratio of the object block so that the line area of a power source current path is changed substantially.
The fifteenth aspect of this invention, in the EMI optimizing method according to 11, characterized in that the step of changing the layout data is to change the block position of the object block so that the line area of a power source current path is changed substantially.
The sixteenth aspect of this invention, in the EMI optimizing method according to the tenth aspect, characterized in that the second step is to invert a direction of one of cell lines each sharing a ground line or power supply line so that a prescribed interval is given between the power line and the ground line adjacent to each other.
The seventeenth aspect of this invention, in the EMI optimizing method according to the tenth aspect, is characterized in that
the second step includes to arrange an auxiliary line connected to a potential between the power supply potential and ground potential above or below a layer where the power line and ground line are formed so that a sum of the capacitances between the power line and ground line, between the ground line and auxiliary line and between the auxiliary line and the power line becomes a desired decoupling capacitance.
The eighteenth aspect of this invention is characterized by comprising the steps of:
sampling blocks or instances with noise in a so high level as to require a measure for EMI in such a manner that an instantaneous current quantity for an object block created when a signal change is generated is computed by execution of simulation, taking into consideration event information inclusive of the name of an instance for each cell of an LSI at issue, name of a signal, timing of the signal change and transient information; and
sorting/displaying the blocks or instances according to the level of noise.
This configuration permits unsuitable portions to be easily detected by sorting the blocks or instance according to the noise level and displaying them, and hence provide good workability.
The nineteenth aspect of this invention is characterized by comprising the steps of:
sampling blocks or instances with noise in so high a level as to require a measure for EMI in such a manner that an instantaneous current quantity for an object block created when a signal change is generated is computed by execution of simulation, taking into consideration event information inclusive of the name of an instance for each cell of an LSI at issue, name of a signal, timing of the signal change and transient information; and
modeling the instantaneous current quantity according to a predetermined rule; and
executing frequency analysis (hereafter called as FFT analysis) of current change information computed by the step of modeling, wherein it further comprises
a step of displaying frequency information acquired in the step of FFT analysis.
The twentieth aspect of this invention, in the EMI analyzing method according to the 19th aspect, is characterized by further comprising the steps of:
highlighting a block to be noticed from the information displayed in the step of displaying;
analyzing EMI information after EMI optimizing processing is executed for the block; and
displaying the information thus analyzed.
The twenty-first aspect of this invention of this invention, in the EMI analyzing method according to the 20th aspect, further comprising the steps of:
storing the optimizing processing as processing historical information; and
displaying the processing historical information as occasion demands.
The simulation is carried out such as by an execution of a logic simulation, and includes the steps of allotting an FFT analysis discrete width to each frequency band and modeling it, and of subjecting the current change information thus computed to fast FFT processing.
The twenty-second aspect of this invention is characterized by comprising the steps of:
deciding a portion with much EMI noise on the basis of an analysis result of EMI noise in an LSI;
displaying the portion which has been decided to have much EMI noise.
In this configuration, the unsuitable portion can be easily detected and also visually observed so that the workability of optimizing can be improved very greatly.
The twenty-third aspect of this invention, in the EMI analyzing method according to the 22nd aspect, is including the step of computing a difference of the portion having a large EMI noise from differences of a plurality of FFT results and displaying it.
In this configuration, the analyzing result is easily understood so that the workability of optimizing is improved.
The twenty-forth aspect of this invention, in the EMI analyzing method according to the 22nd aspect, characterized in that the step of displaying includes to display two FFT results so that differences of specified portions of any shape are displayed in different colors for the color identification of the differences of a shape.
In this configuration, the analyzing result is easily understood so that the workability of optimizing is improved.
The twenty-fifth aspect of this invention, in the EMI analyzing method according to the 22nd aspect, is characterized in that the step of deciding includes to compute the differences on the basis of information of circuit portions sorted according to the degree of noise.
In this configuration, the information is sorted according to the degree of noise so that the computing can be easily carried out with good workability.
The twenty-sixth aspect of this invention, in the EMI analyzing method according to the 22nd aspect, is characterized in that the step of displaying includes to display the portions in color identification between circuit diagram information and layout information or by character information.
In this configuration, the workability of optimizing is improved greatly.
The twenty-seventh aspect of this invention, in the EMI analyzing method, is characterized by further comprising the steps of:
analyzing EMI information of a portion EMI-optimized for the block; and
displaying the analyzed information.
In this configuration, the optimized portion is further analyzed so that the result can be satisfied one such as a good workability.